// Generated for: spectre
// Generated on: Apr 29 04:19:38 2008
// Design library name: Project
// Design cell name: TB_ALUadd
// Design view name: schematic
simulator lang=spectre
global 0 vdd!

// Library name: Project
// Cell name: inv_4X
// View name: schematic
subckt inv_4X VDD VSS in out
    MN (out in VSS VSS) ami06N w=6u l=600n as=9e-12 ad=9e-12 ps=15.0u \
        pd=15.0u m=1 region=sat
    MP (out in VDD VDD) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
ends inv_4X
// End of subcircuit definition.

// Library name: Project
// Cell name: inv
// View name: schematic
subckt inv VDD VSS in out
    MN (out in VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 ps=6u \
        pd=6u m=1 region=sat
    MP (out in VDD VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
ends inv
// End of subcircuit definition.

// Library name: Project
// Cell name: inv_2X
// View name: schematic
subckt inv_2X VDD VSS in out
    MN (out in VSS VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    MP (out in VDD VDD) ami06P w=6u l=600n as=9e-12 ad=9e-12 ps=15.0u \
        pd=15.0u m=1 region=sat
ends inv_2X
// End of subcircuit definition.

// Library name: Project
// Cell name: Register_pos_small
// View name: schematic
subckt Register_pos_small CLK D Q1 Q2 VDD VSS
    I0 (VDD VSS CLK CLKB) inv_4X
    I2 (VDD VSS net31 Q2) inv
    I1 (VDD VSS net35 Q1) inv_2X
    N7 (net19 Q2 VSS VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N6 (net31 CLKB net19 net19) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 \
        ps=9u pd=9u m=1 region=sat
    N5 (net27 Q1 VSS VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N0 (net31 CLK net27 net27) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 \
        ps=9u pd=9u m=1 region=sat
    N1 (net35 CLKB net39 net39) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 \
        ps=9u pd=9u m=1 region=sat
    N2 (net39 D VSS VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N4 (net43 Q1 VSS VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N3 (net35 CLK net43 net43) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 \
        ps=9u pd=9u m=1 region=sat
    P7 (net31 CLK net52 net52) ami06P w=6u l=600n as=9e-12 ad=9e-12 \
        ps=15.0u pd=15.0u m=1 region=sat
    P6 (net52 Q2 VDD VDD) ami06P w=6uM l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    P5 (net31 CLKB net60 net60) ami06P w=6u l=600n as=9e-12 ad=9e-12 \
        ps=15.0u pd=15.0u m=1 region=sat
    P0 (net60 Q1 VDD VDD) ami06P w=6u l=600n as=9e-12 ad=9e-12 ps=15.0u \
        pd=15.0u m=1 region=sat
    P1 (net35 CLK net68 net68) ami06P w=6u l=600n as=9e-12 ad=9e-12 \
        ps=15.0u pd=15.0u m=1 region=sat
    P2 (net68 D VDD VDD) ami06P w=6u l=600n as=9e-12 ad=9e-12 ps=15.0u \
        pd=15.0u m=1 region=sat
    P3 (net35 CLKB net76 net76) ami06P w=6u l=600n as=9e-12 ad=9e-12 \
        ps=15.0u pd=15.0u m=1 region=sat
    P4 (net76 Q1 VDD VDD) ami06P w=6u l=600n as=9e-12 ad=9e-12 ps=15.0u \
        pd=15.0u m=1 region=sat
ends Register_pos_small
// End of subcircuit definition.

// Library name: Project
// Cell name: Register_pos_test
// View name: schematic
subckt Register_pos_test CLK D Q1 Q2 VDD VSS
    I0 (VDD VSS CLK CLKB) inv
    I1 (VDD VSS net35 Q1) inv
    I2 (VDD VSS net31 Q2) inv_4X
    N7 (net19 Q2 VSS VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N6 (net31 CLKB net19 net19) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 \
        ps=9u pd=9u m=1 region=sat
    N5 (net27 Q1 VSS VSS) ami06N w=4.5u l=600n as=6.75e-12 ad=6.75e-12 \
        ps=12.0u pd=12.0u m=1 region=sat
    N0 (net31 CLK net27 net27) ami06N w=4.5u l=600n as=6.75e-12 \
        ad=6.75e-12 ps=12.0u pd=12.0u m=1 region=sat
    N1 (net35 CLKB net39 net39) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 \
        ps=9u pd=9u m=1 region=sat
    N2 (net39 D VSS VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N4 (net43 Q1 VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    N3 (net35 CLK net43 net43) ami06N w=1.5u l=600n as=2.25e-12 \
        ad=2.25e-12 ps=6u pd=6u m=1 region=sat
    P7 (net31 CLK net52 net52) ami06P w=6u l=600n as=9e-12 ad=9e-12 \
        ps=15.0u pd=15.0u m=1 region=sat
    P6 (net52 Q2 VDD VDD) ami06P w=6u l=600n as=9e-12 ad=9e-12 ps=15.0u \
        pd=15.0u m=1 region=sat
    P5 (net31 CLKB net60 net60) ami06P w=9u l=600n as=1.35e-11 ad=1.35e-11 \
        ps=21.0u pd=21.0u m=1 region=sat
    P0 (net60 Q1 VDD VDD) ami06P w=9u l=600n as=1.35e-11 ad=1.35e-11 \
        ps=21.0u pd=21.0u m=1 region=sat
    P1 (net35 CLK net68 net68) ami06P w=6u l=600n as=9e-12 ad=9e-12 \
        ps=15.0u pd=15.0u m=1 region=sat
    P2 (net68 D VDD VDD) ami06P w=6u l=600n as=9e-12 ad=9e-12 ps=15.0u \
        pd=15.0u m=1 region=sat
    P3 (net35 CLKB net76 net76) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 \
        ps=9u pd=9u m=1 region=sat
    P4 (net76 Q1 VDD VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
ends Register_pos_test
// End of subcircuit definition.

// Library name: Project
// Cell name: tgateSimple_min
// View name: schematic
subckt tgateSimple_min VDD VSS in out pass passB
    P0 (out passB in VDD) ami06P w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    N0 (in pass out VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
ends tgateSimple_min
// End of subcircuit definition.

// Library name: Project
// Cell name: OR_min
// View name: schematic
subckt OR_min OUT VDD VSS inA inB
    N2 (OUT net026 VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    N0 (net026 inA VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    N1 (net026 inB VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    P1 (net026 inB net20 VDD) ami06P w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    P2 (OUT net026 VDD VDD) ami06P w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    P0 (net20 inA VDD VDD) ami06P w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
ends OR_min
// End of subcircuit definition.

// Library name: Project
// Cell name: OR16A
// View name: schematic
subckt OR16A OUT_0 OUT_1 OUT_2 OUT_3 OUT_4 OUT_5 OUT_6 OUT_7 OUT_8 OUT_9 \
        OUT_10 OUT_11 OUT_12 OUT_13 OUT_14 OUT_15 VDD VSS inA_0 inA_1 \
        inA_2 inA_3 inA_4 inA_5 inA_6 inA_7 inA_8 inA_9 inA_10 inA_11 \
        inA_12 inA_13 inA_14 inA_15 inB_0 inB_1 inB_2 inB_3 inB_4 inB_5 \
        inB_6 inB_7 inB_8 inB_9 inB_10 inB_11 inB_12 inB_13 inB_14 inB_15 \
        pass passB
    I7_0 (VDD VSS net35_0 OUT_0 pass passB) tgateSimple_min
    I7_1 (VDD VSS net35_1 OUT_1 pass passB) tgateSimple_min
    I7_2 (VDD VSS net35_2 OUT_2 pass passB) tgateSimple_min
    I7_3 (VDD VSS net35_3 OUT_3 pass passB) tgateSimple_min
    I7_4 (VDD VSS net35_4 OUT_4 pass passB) tgateSimple_min
    I7_5 (VDD VSS net35_5 OUT_5 pass passB) tgateSimple_min
    I7_6 (VDD VSS net35_6 OUT_6 pass passB) tgateSimple_min
    I7_7 (VDD VSS net35_7 OUT_7 pass passB) tgateSimple_min
    I7_8 (VDD VSS net35_8 OUT_8 pass passB) tgateSimple_min
    I7_9 (VDD VSS net35_9 OUT_9 pass passB) tgateSimple_min
    I7_10 (VDD VSS net35_10 OUT_10 pass passB) tgateSimple_min
    I7_11 (VDD VSS net35_11 OUT_11 pass passB) tgateSimple_min
    I7_12 (VDD VSS net35_12 OUT_12 pass passB) tgateSimple_min
    I7_13 (VDD VSS net35_13 OUT_13 pass passB) tgateSimple_min
    I7_14 (VDD VSS net35_14 OUT_14 pass passB) tgateSimple_min
    I7_15 (VDD VSS net35_15 OUT_15 pass passB) tgateSimple_min
    OR_tgate_0 (VDD VSS inA_0 net24_0 pass passB) tgateSimple_min
    OR_tgate_1 (VDD VSS inA_1 net24_1 pass passB) tgateSimple_min
    OR_tgate_2 (VDD VSS inA_2 net24_2 pass passB) tgateSimple_min
    OR_tgate_3 (VDD VSS inA_3 net24_3 pass passB) tgateSimple_min
    OR_tgate_4 (VDD VSS inA_4 net24_4 pass passB) tgateSimple_min
    OR_tgate_5 (VDD VSS inA_5 net24_5 pass passB) tgateSimple_min
    OR_tgate_6 (VDD VSS inA_6 net24_6 pass passB) tgateSimple_min
    OR_tgate_7 (VDD VSS inA_7 net24_7 pass passB) tgateSimple_min
    OR_tgate_8 (VDD VSS inA_8 net24_8 pass passB) tgateSimple_min
    OR_tgate_9 (VDD VSS inA_9 net24_9 pass passB) tgateSimple_min
    OR_tgate_10 (VDD VSS inA_10 net24_10 pass passB) tgateSimple_min
    OR_tgate_11 (VDD VSS inA_11 net24_11 pass passB) tgateSimple_min
    OR_tgate_12 (VDD VSS inA_12 net24_12 pass passB) tgateSimple_min
    OR_tgate_13 (VDD VSS inA_13 net24_13 pass passB) tgateSimple_min
    OR_tgate_14 (VDD VSS inA_14 net24_14 pass passB) tgateSimple_min
    OR_tgate_15 (VDD VSS inA_15 net24_15 pass passB) tgateSimple_min
    I6_0 (VDD VSS inB_0 net30_0 pass passB) tgateSimple_min
    I6_1 (VDD VSS inB_1 net30_1 pass passB) tgateSimple_min
    I6_2 (VDD VSS inB_2 net30_2 pass passB) tgateSimple_min
    I6_3 (VDD VSS inB_3 net30_3 pass passB) tgateSimple_min
    I6_4 (VDD VSS inB_4 net30_4 pass passB) tgateSimple_min
    I6_5 (VDD VSS inB_5 net30_5 pass passB) tgateSimple_min
    I6_6 (VDD VSS inB_6 net30_6 pass passB) tgateSimple_min
    I6_7 (VDD VSS inB_7 net30_7 pass passB) tgateSimple_min
    I6_8 (VDD VSS inB_8 net30_8 pass passB) tgateSimple_min
    I6_9 (VDD VSS inB_9 net30_9 pass passB) tgateSimple_min
    I6_10 (VDD VSS inB_10 net30_10 pass passB) tgateSimple_min
    I6_11 (VDD VSS inB_11 net30_11 pass passB) tgateSimple_min
    I6_12 (VDD VSS inB_12 net30_12 pass passB) tgateSimple_min
    I6_13 (VDD VSS inB_13 net30_13 pass passB) tgateSimple_min
    I6_14 (VDD VSS inB_14 net30_14 pass passB) tgateSimple_min
    I6_15 (VDD VSS inB_15 net30_15 pass passB) tgateSimple_min
    I0_0 (net35_0 VDD VSS net24_0 net30_0) OR_min
    I0_1 (net35_1 VDD VSS net24_1 net30_1) OR_min
    I0_2 (net35_2 VDD VSS net24_2 net30_2) OR_min
    I0_3 (net35_3 VDD VSS net24_3 net30_3) OR_min
    I0_4 (net35_4 VDD VSS net24_4 net30_4) OR_min
    I0_5 (net35_5 VDD VSS net24_5 net30_5) OR_min
    I0_6 (net35_6 VDD VSS net24_6 net30_6) OR_min
    I0_7 (net35_7 VDD VSS net24_7 net30_7) OR_min
    I0_8 (net35_8 VDD VSS net24_8 net30_8) OR_min
    I0_9 (net35_9 VDD VSS net24_9 net30_9) OR_min
    I0_10 (net35_10 VDD VSS net24_10 net30_10) OR_min
    I0_11 (net35_11 VDD VSS net24_11 net30_11) OR_min
    I0_12 (net35_12 VDD VSS net24_12 net30_12) OR_min
    I0_13 (net35_13 VDD VSS net24_13 net30_13) OR_min
    I0_14 (net35_14 VDD VSS net24_14 net30_14) OR_min
    I0_15 (net35_15 VDD VSS net24_15 net30_15) OR_min
ends OR16A
// End of subcircuit definition.

// Library name: Project
// Cell name: inv_8X
// View name: schematic
subckt inv_8X VDD VSS in out
    MN (out in VSS VSS) ami06N w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    MP (out in VDD VDD) ami06P w=24.0u l=600n as=3.6e-11 ad=3.6e-11 \
        ps=51.0u pd=51.0u m=1 region=sat
ends inv_8X
// End of subcircuit definition.

// Library name: Project
// Cell name: NAND2_big
// View name: schematic
subckt NAND2_big VDD VSS in1 in2 out
    N0 (net6 in2 VSS VSS) ami06N w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    MN (out in1 net6 VSS) ami06N w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    P0 (out in2 VDD VDD) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    MP (out in1 VDD VDD) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
ends NAND2_big
// End of subcircuit definition.

// Library name: Project
// Cell name: tgateSimple
// View name: schematic
subckt tgateSimple VDD VSS in out pass passB
    P0 (out passB in VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N0 (in pass out VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
ends tgateSimple
// End of subcircuit definition.

// Library name: Project
// Cell name: XOR
// View name: schematic
subckt XOR VDD VSS in1 in2 xor
    I7 (VDD VSS invertedin bufferedin) inv
    I0 (VDD VSS in2 invertedin) inv
    I8 (VDD VSS bufferedin xor in1B in1) tgateSimple
    I9 (VDD VSS invertedin xor in1 in1B) tgateSimple
    I10 (VDD VSS in1 in1B) inv_4X
ends XOR
// End of subcircuit definition.

// Library name: Project
// Cell name: NAND2
// View name: schematic
subckt NAND2 VDD VSS in1 in2 out
    N0 (net6 in2 VSS VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    MN (out in1 net6 VSS) ami06N w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    P0 (out in2 VDD VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    MP (out in1 VDD VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
ends NAND2
// End of subcircuit definition.

// Library name: Project
// Cell name: AND
// View name: schematic
subckt AND A B VDD VSS out outB
    I0 (VDD VSS outB out) inv
    _inst0 (VDD VSS A B outB) NAND2
ends AND
// End of subcircuit definition.

// Library name: Project
// Cell name: OR
// View name: schematic
subckt OR OUT VDD VSS inA inB
    N2 (OUT net026 VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    N0 (net026 inA VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    N1 (net026 inB VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    P1 (net026 inB net20 VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 \
        ps=9u pd=9u m=1 region=sat
    P2 (OUT net026 VDD VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    P0 (net20 inA VDD VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
ends OR
// End of subcircuit definition.

// Library name: Project
// Cell name: XNOR
// View name: schematic
subckt XNOR VDD VSS in1 in2 xnor
    I2 (VDD VSS in1 in1B) inv_4X
    I3 (VDD VSS in2 xnor in1 in1B) tgateSimple
    I4 (VDD VSS net25 xnor in1B in1) tgateSimple
    I1 (VDD VSS in2 net25) inv
ends XNOR
// End of subcircuit definition.

// Library name: Project
// Cell name: tgate_add
// View name: schematic
subckt tgate_add VDD VSS in out pass
    I3 (VDD VSS pass pass_inv) inv
    N0 (in pass out VSS) ami06N w=6u l=600n as=9e-12 ad=9e-12 ps=15.0u \
        pd=15.0u m=1 region=sat
    P0 (out pass_inv in VDD) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
ends tgate_add
// End of subcircuit definition.

// Library name: Project
// Cell name: add1b_invC
// View name: schematic
subckt add1b_invC Cin propagate Sum VDD VSS in1 in2
    I4 (in1 in2 VDD VSS kill net052) AND
    I1 (generate VDD VSS in1 in2) OR
    I0 (VDD VSS xorAB Cin Sum) XNOR
    P1 (propagate generate VDD VDD) ami06P w=3u l=600n as=4.5e-12 \
        ad=4.5e-12 ps=9u pd=9u m=1 region=sat
    N1 (propagate kill VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 \
        ad=2.25e-12 ps=6u pd=6u m=1 region=sat
    I6 (VDD VSS in2 in1 xorAB) XOR
    I3 (VDD VSS Cin propagate xorAB) tgate_add
ends add1b_invC
// End of subcircuit definition.

// Library name: Project
// Cell name: NOR
// View name: schematic
subckt NOR VDD VSS inA inB out
    P0 (net6 inA VDD VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    P1 (out inB net6 VDD) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N1 (out inB VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
    N0 (out inA VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 ad=2.25e-12 \
        ps=6u pd=6u m=1 region=sat
ends NOR
// End of subcircuit definition.

// Library name: Project
// Cell name: add1b
// View name: schematic
subckt add1b Cin propagate Sum VDD VSS in1 in2
    I3 (VDD VSS Cin propagate xorAB) tgate_add
    I8 (VDD VSS in1 in2 generate) NAND2
    I7 (VDD VSS xorAB Cin Sum) XOR
    I6 (VDD VSS in2 in1 xorAB) XOR
    I5 (VDD VSS in1 in2 kill) NOR
    N1 (propagate kill VSS VSS) ami06N w=1.5u l=600n as=2.25e-12 \
        ad=2.25e-12 ps=6u pd=6u m=1 region=sat
    P1 (propagate generate VDD VDD) ami06P w=3u l=600n as=4.5e-12 \
        ad=4.5e-12 ps=9u pd=9u m=1 region=sat
ends add1b
// End of subcircuit definition.

// Library name: Project
// Cell name: add16b_inv
// View name: schematic
subckt add16b_inv A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 \
        A_13 A_14 A_15 B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_10 B_11 \
        B_12 B_13 B_14 B_15 Cin0 Cout_0 Cout_1 Cout_2 Cout_3 Cout_4 Cout_5 \
        Cout_6 Cout_7 Cout_8 Cout_9 Cout_10 Cout_11 Cout_12 Cout_13 \
        Cout_14 Cout_15 Sum_0 Sum_1 Sum_2 Sum_3 Sum_4 Sum_5 Sum_6 Sum_7 \
        Sum_8 Sum_9 Sum_10 Sum_11 Sum_12 Sum_13 Sum_14 Sum_15 VDD VSS
    I12 (VDD VSS Cout_3 invCout3) inv_4X
    I13 (VDD VSS Cout_7 invCout7) inv_4X
    I14 (VDD VSS Cout_11 invCout11) inv_4X
    I11_0 (invCout3 Cout_4 Sum_4 VDD VSS A_4 B_4) add1b_invC
    I11_1 (Cout_4 Cout_5 Sum_5 VDD VSS A_5 B_5) add1b_invC
    I11_2 (Cout_5 Cout_6 Sum_6 VDD VSS A_6 B_6) add1b_invC
    I11_3 (Cout_6 Cout_7 Sum_7 VDD VSS A_7 B_7) add1b_invC
    I11_4 (invCout11 Cout_12 Sum_12 VDD VSS A_12 B_12) add1b_invC
    I11_5 (Cout_12 Cout_13 Sum_13 VDD VSS A_13 B_13) add1b_invC
    I11_6 (Cout_13 Cout_14 Sum_14 VDD VSS A_14 B_14) add1b_invC
    I11_7 (Cout_14 Cout_15 Sum_15 VDD VSS A_15 B_15) add1b_invC
    I0_0 (Cin0 Cout_0 Sum_0 VDD VSS A_0 B_0) add1b
    I0_1 (Cout_0 Cout_1 Sum_1 VDD VSS A_1 B_1) add1b
    I0_2 (Cout_1 Cout_2 Sum_2 VDD VSS A_2 B_2) add1b
    I0_3 (Cout_2 Cout_3 Sum_3 VDD VSS A_3 B_3) add1b
    I0_4 (invCout7 Cout_8 Sum_8 VDD VSS A_8 B_8) add1b
    I0_5 (Cout_8 Cout_9 Sum_9 VDD VSS A_9 B_9) add1b
    I0_6 (Cout_9 Cout_10 Sum_10 VDD VSS A_10 B_10) add1b
    I0_7 (Cout_10 Cout_11 Sum_11 VDD VSS A_11 B_11) add1b
ends add16b_inv
// End of subcircuit definition.

// Library name: Project
// Cell name: addsub16b_block
// View name: schematic
subckt addsub16b_block A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 \
        A_12 A_13 A_14 A_15 B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_10 \
        B_11 B_12 B_13 B_14 B_15 Control Cout_0 Cout_1 Cout_2 Cout_3 \
        Cout_4 Cout_5 Cout_6 Cout_7 Cout_8 Cout_9 Cout_10 Cout_11 Cout_12 \
        Cout_13 Cout_14 Cout_15 Sum_0 Sum_1 Sum_2 Sum_3 Sum_4 Sum_5 Sum_6 \
        Sum_7 Sum_8 Sum_9 Sum_10 Sum_11 Sum_12 Sum_13 Sum_14 Sum_15 VDD \
        VSS
    I0 (A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 A_13 A_14 \
        A_15 net19_0 net19_1 net19_2 net19_3 net19_4 net19_5 net19_6 \
        net19_7 net19_8 net19_9 net19_10 net19_11 net19_12 net19_13 \
        net19_14 net19_15 Control Cout_0 Cout_1 Cout_2 Cout_3 Cout_4 \
        Cout_5 Cout_6 Cout_7 Cout_8 Cout_9 Cout_10 Cout_11 Cout_12 Cout_13 \
        Cout_14 Cout_15 Sum_0 Sum_1 Sum_2 Sum_3 Sum_4 Sum_5 Sum_6 Sum_7 \
        Sum_8 Sum_9 Sum_10 Sum_11 Sum_12 Sum_13 Sum_14 Sum_15 VDD VSS) \
        add16b_inv
    I1_0 (VDD VSS B_0 Control net19_0) XOR
    I1_1 (VDD VSS B_1 Control net19_1) XOR
    I1_2 (VDD VSS B_2 Control net19_2) XOR
    I1_3 (VDD VSS B_3 Control net19_3) XOR
    I1_4 (VDD VSS B_4 Control net19_4) XOR
    I1_5 (VDD VSS B_5 Control net19_5) XOR
    I1_6 (VDD VSS B_6 Control net19_6) XOR
    I1_7 (VDD VSS B_7 Control net19_7) XOR
    I1_8 (VDD VSS B_8 Control net19_8) XOR
    I1_9 (VDD VSS B_9 Control net19_9) XOR
    I1_10 (VDD VSS B_10 Control net19_10) XOR
    I1_11 (VDD VSS B_11 Control net19_11) XOR
    I1_12 (VDD VSS B_12 Control net19_12) XOR
    I1_13 (VDD VSS B_13 Control net19_13) XOR
    I1_14 (VDD VSS B_14 Control net19_14) XOR
    I1_15 (VDD VSS B_15 Control net19_15) XOR
ends addsub16b_block
// End of subcircuit definition.

// Library name: Project
// Cell name: Shift1b
// View name: schematic
subckt Shift1b A LSB0 LSB1 LSB2 LSB3 SH_0 SH_1 SH_2 SH_3 SHB_0 SHB_1 SHB_2 \
        SHB_3 VDD VSS
    I2 (VDD VSS LSB2 A SH_2 SHB_2) tgateSimple
    I1 (VDD VSS LSB0 A SH_0 SHB_0) tgateSimple
    I0 (VDD VSS LSB3 A SH_3 SHB_3) tgateSimple
    I3 (VDD VSS LSB1 A SH_1 SHB_1) tgateSimple
ends Shift1b
// End of subcircuit definition.

// Library name: Project
// Cell name: 2:4_decoder
// View name: schematic
subckt _sub2 VDD VSS out_0 out_1 out_2 out_3 sel0 sel1 outB_0 outB_1 \
        outB_2 outB_3
    I9 (VDD VSS sel1 sel0 outB_3) NAND2
    I6 (VDD VSS sel1 sel1B outB_2) NAND2
    I4 (VDD VSS sel0B sel0 outB_1) NAND2
    I2 (VDD VSS sel0B sel1B outB_0) NAND2
    I10 (VDD VSS outB_3 out_3) inv
    I7 (VDD VSS outB_2 out_2) inv
    I5 (VDD VSS outB_1 out_1) inv
    I3 (VDD VSS outB_0 out_0) inv
    I8 (VDD VSS sel1 sel0B) inv
    I1 (VDD VSS sel0 sel1B) inv
ends _sub2
// End of subcircuit definition.

// Library name: Project
// Cell name: Shift4b
// View name: schematic
subckt Shift4b A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 A_13 \
        A_14 ASHIFT_0 ASHIFT_1 ASHIFT_2 ASHIFT_3 ASHIFT_4 ASHIFT_5 \
        ASHIFT_6 ASHIFT_7 ASHIFT_8 ASHIFT_9 ASHIFT_10 ASHIFT_11 ASHIFT_12 \
        ASHIFT_13 ASHIFT_14 ASHIFT_15 B0 B1 VDD VSS pass passB
    shift_tgate_0 (VDD VSS outShift_0 ASHIFT_0 pass passB) tgateSimple_min
    shift_tgate_1 (VDD VSS outShift_1 ASHIFT_1 pass passB) tgateSimple_min
    shift_tgate_2 (VDD VSS outShift_2 ASHIFT_2 pass passB) tgateSimple_min
    shift_tgate_3 (VDD VSS outShift_3 ASHIFT_3 pass passB) tgateSimple_min
    shift_tgate_4 (VDD VSS outShift_4 ASHIFT_4 pass passB) tgateSimple_min
    shift_tgate_5 (VDD VSS outShift_5 ASHIFT_5 pass passB) tgateSimple_min
    shift_tgate_6 (VDD VSS outShift_6 ASHIFT_6 pass passB) tgateSimple_min
    shift_tgate_7 (VDD VSS outShift_7 ASHIFT_7 pass passB) tgateSimple_min
    shift_tgate_8 (VDD VSS outShift_8 ASHIFT_8 pass passB) tgateSimple_min
    shift_tgate_9 (VDD VSS outShift_9 ASHIFT_9 pass passB) tgateSimple_min
    shift_tgate_10 (VDD VSS outShift_10 ASHIFT_10 pass passB) \
        tgateSimple_min
    shift_tgate_11 (VDD VSS outShift_11 ASHIFT_11 pass passB) \
        tgateSimple_min
    shift_tgate_12 (VDD VSS outShift_12 ASHIFT_12 pass passB) \
        tgateSimple_min
    shift_tgate_13 (VDD VSS outShift_13 ASHIFT_13 pass passB) \
        tgateSimple_min
    shift_tgate_14 (VDD VSS outShift_14 ASHIFT_14 pass passB) \
        tgateSimple_min
    shift_tgate_15 (VDD VSS outShift_15 ASHIFT_15 pass passB) \
        tgateSimple_min
    I0_0 (outShift_0 VSS VSS VSS VSS shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_1 (outShift_1 A_0 VSS VSS VSS shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_2 (outShift_2 A_1 A_0 VSS VSS shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_3 (outShift_3 A_2 A_1 A_0 VSS shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_4 (outShift_4 A_3 A_2 A_1 A_0 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_5 (outShift_5 A_4 A_3 A_2 A_1 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_6 (outShift_6 A_5 A_4 A_3 A_2 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_7 (outShift_7 A_6 A_5 A_4 A_3 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_8 (outShift_8 A_7 A_6 A_5 A_4 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_9 (outShift_9 A_8 A_7 A_6 A_5 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_10 (outShift_10 A_9 A_8 A_7 A_6 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_11 (outShift_11 A_10 A_9 A_8 A_7 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_12 (outShift_12 A_11 A_10 A_9 A_8 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_13 (outShift_13 A_12 A_11 A_10 A_9 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_14 (outShift_14 A_13 A_12 A_11 A_10 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I0_15 (outShift_15 A_14 A_13 A_12 A_11 shiftInDecode_0 shiftInDecode_1 \
        shiftInDecode_2 shiftInDecode_3 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3 VDD VSS) Shift1b
    I4 (VDD VSS shiftInDecode_0 shiftInDecode_1 shiftInDecode_2 \
        shiftInDecode_3 B0 B1 shiftInDecodeB_0 shiftInDecodeB_1 \
        shiftInDecodeB_2 shiftInDecodeB_3) _sub2
ends Shift4b
// End of subcircuit definition.

// Library name: Project
// Cell name: inv_fastlow
// View name: schematic
subckt inv_fastlow VDD VSS in out
    MN (out in VSS VSS) ami06N w=24.0u l=600n as=3.6e-11 ad=3.6e-11 \
        ps=51.0u pd=51.0u m=1 region=sat
    MP (out in VDD VDD) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
ends inv_fastlow
// End of subcircuit definition.

// Library name: Project
// Cell name: NAND3_med
// View name: schematic
subckt NAND3_med Gnd Vdd in0 in1 in2 out
    P1 (out in2 Vdd Vdd) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    P2 (out in1 Vdd Vdd) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    P3 (out in0 Vdd Vdd) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    N1 (out in2 net21 Gnd) ami06N w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    N2 (net21 in1 net24 Gnd) ami06N w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    N3 (net24 in0 Gnd Gnd) ami06N w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
ends NAND3_med
// End of subcircuit definition.

// Library name: Project
// Cell name: inv_6X
// View name: schematic
subckt inv_6X VDD VSS in out
    MN (out in VSS VSS) ami06N w=9u l=600n as=1.35e-11 ad=1.35e-11 \
        ps=21.0u pd=21.0u m=1 region=sat
    MP (out in VDD VDD) ami06P w=18.0u l=600n as=2.7e-11 ad=2.7e-11 \
        ps=39.0u pd=39.0u m=1 region=sat
ends inv_6X
// End of subcircuit definition.

// Library name: Project
// Cell name: NAND3
// View name: schematic
subckt NAND3 Gnd Vdd in0 in1 in2 out
    P1 (out in2 Vdd Vdd) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    P2 (out in1 Vdd Vdd) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    P3 (out in0 Vdd Vdd) ami06P w=3u l=600n as=4.5e-12 ad=4.5e-12 ps=9u \
        pd=9u m=1 region=sat
    N1 (out in2 net21 Gnd) ami06N w=4.05u l=600n as=6.075e-12 ad=6.075e-12 \
        ps=11.1u pd=11.1u m=1 region=sat
    N2 (net21 in1 net24 Gnd) ami06N w=4.05u l=600n as=6.075e-12 \
        ad=6.075e-12 ps=11.1u pd=11.1u m=1 region=sat
    N3 (net24 in0 Gnd Gnd) ami06N w=4.05u l=600n as=6.075e-12 ad=6.075e-12 \
        ps=11.1u pd=11.1u m=1 region=sat
ends NAND3
// End of subcircuit definition.

// Library name: Project
// Cell name: NAND3_big
// View name: schematic
subckt NAND3_big Gnd Vdd in0 in1 in2 out
    P1 (out in2 Vdd Vdd) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    P2 (out in1 Vdd Vdd) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    P3 (out in0 Vdd Vdd) ami06P w=12.0u l=600n as=1.8e-11 ad=1.8e-11 \
        ps=27.0u pd=27.0u m=1 region=sat
    N1 (out in2 net21 Gnd) ami06N w=19.95u l=600n as=2.9925e-11 \
        ad=2.9925e-11 ps=42.9u pd=42.9u m=1 region=sat
    N2 (net21 in1 net24 Gnd) ami06N w=19.95u l=600n as=2.9925e-11 \
        ad=2.9925e-11 ps=42.9u pd=42.9u m=1 region=sat
    N3 (net24 in0 Gnd Gnd) ami06N w=19.95u l=600n as=2.9925e-11 \
        ad=2.9925e-11 ps=42.9u pd=42.9u m=1 region=sat
ends NAND3_big
// End of subcircuit definition.

// Library name: Project
// Cell name: 3:8_decoder
// View name: schematic
subckt _sub3 A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 Abar_0 Abar_1 Abar_2 Abar_3 \
        Abar_4 Abar_5 Abar_6 Abar_7 VDD VSS sel0 sel1 sel2
    I23 (VDD VSS Abar_5 A_5) inv_fastlow
    I21 (VDD VSS Abar_3 A_3) inv_fastlow
    I22 (VDD VSS Abar_4 A_4) inv_fastlow
    I24 (VDD VSS Abar_6 A_6) inv_fastlow
    I3 (VDD VSS Abar_0 A_0) inv_fastlow
    I25 (VDD VSS Abar_7 A_7) inv_fastlow
    I15 (VSS VDD sel2 sel0B sel1 Abar_6) NAND3_med
    I16 (VSS VDD sel2 sel1 sel0 Abar_7) NAND3_med
    I17 (VSS VDD sel2 sel0 sel1B Abar_5) NAND3_med
    I18 (VSS VDD sel2 sel0B sel1B Abar_4) NAND3_med
    I9 (VSS VDD sel1 sel0 sel2B Abar_3) NAND3_med
    I0 (VSS VDD sel0B sel1B sel2B Abar_0) NAND3_med
    I1 (VDD VSS sel1 sel1B) inv_6X
    I5 (VSS VDD sel1B sel2B sel0 Abar_1) NAND3
    I19 (VDD VSS Abar_1 A_1) inv_2X
    I20 (VDD VSS Abar_2 A_2) inv_8X
    I2 (VDD VSS sel2 sel2B) inv_8X
    I8 (VDD VSS sel0 sel0B) inv_8X
    I10 (VSS VDD sel0B sel1 sel2B Abar_2) NAND3_big
ends _sub3
// End of subcircuit definition.

// Library name: Project
// Cell name: AND16A
// View name: schematic
subckt AND16A A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 A_13 \
        A_14 A_15 B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_10 B_11 B_12 \
        B_13 B_14 B_15 VDD VSS out_0 out_1 out_2 out_3 out_4 out_5 out_6 \
        out_7 out_8 out_9 out_10 out_11 out_12 out_13 out_14 out_15 pass \
        passB
    B_tgate_0 (VDD VSS B_0 net27_0 pass passB) tgateSimple_min
    B_tgate_1 (VDD VSS B_1 net27_1 pass passB) tgateSimple_min
    B_tgate_2 (VDD VSS B_2 net27_2 pass passB) tgateSimple_min
    B_tgate_3 (VDD VSS B_3 net27_3 pass passB) tgateSimple_min
    B_tgate_4 (VDD VSS B_4 net27_4 pass passB) tgateSimple_min
    B_tgate_5 (VDD VSS B_5 net27_5 pass passB) tgateSimple_min
    B_tgate_6 (VDD VSS B_6 net27_6 pass passB) tgateSimple_min
    B_tgate_7 (VDD VSS B_7 net27_7 pass passB) tgateSimple_min
    B_tgate_8 (VDD VSS B_8 net27_8 pass passB) tgateSimple_min
    B_tgate_9 (VDD VSS B_9 net27_9 pass passB) tgateSimple_min
    B_tgate_10 (VDD VSS B_10 net27_10 pass passB) tgateSimple_min
    B_tgate_11 (VDD VSS B_11 net27_11 pass passB) tgateSimple_min
    B_tgate_12 (VDD VSS B_12 net27_12 pass passB) tgateSimple_min
    B_tgate_13 (VDD VSS B_13 net27_13 pass passB) tgateSimple_min
    B_tgate_14 (VDD VSS B_14 net27_14 pass passB) tgateSimple_min
    B_tgate_15 (VDD VSS B_15 net27_15 pass passB) tgateSimple_min
    AND_tgate_0 (VDD VSS out_and_0 out_0 pass passB) tgateSimple_min
    AND_tgate_1 (VDD VSS out_and_1 out_1 pass passB) tgateSimple_min
    AND_tgate_2 (VDD VSS out_and_2 out_2 pass passB) tgateSimple_min
    AND_tgate_3 (VDD VSS out_and_3 out_3 pass passB) tgateSimple_min
    AND_tgate_4 (VDD VSS out_and_4 out_4 pass passB) tgateSimple_min
    AND_tgate_5 (VDD VSS out_and_5 out_5 pass passB) tgateSimple_min
    AND_tgate_6 (VDD VSS out_and_6 out_6 pass passB) tgateSimple_min
    AND_tgate_7 (VDD VSS out_and_7 out_7 pass passB) tgateSimple_min
    AND_tgate_8 (VDD VSS out_and_8 out_8 pass passB) tgateSimple_min
    AND_tgate_9 (VDD VSS out_and_9 out_9 pass passB) tgateSimple_min
    AND_tgate_10 (VDD VSS out_and_10 out_10 pass passB) tgateSimple_min
    AND_tgate_11 (VDD VSS out_and_11 out_11 pass passB) tgateSimple_min
    AND_tgate_12 (VDD VSS out_and_12 out_12 pass passB) tgateSimple_min
    AND_tgate_13 (VDD VSS out_and_13 out_13 pass passB) tgateSimple_min
    AND_tgate_14 (VDD VSS out_and_14 out_14 pass passB) tgateSimple_min
    AND_tgate_15 (VDD VSS out_and_15 out_15 pass passB) tgateSimple_min
    A_tgate_0 (VDD VSS A_0 net33_0 pass passB) tgateSimple_min
    A_tgate_1 (VDD VSS A_1 net33_1 pass passB) tgateSimple_min
    A_tgate_2 (VDD VSS A_2 net33_2 pass passB) tgateSimple_min
    A_tgate_3 (VDD VSS A_3 net33_3 pass passB) tgateSimple_min
    A_tgate_4 (VDD VSS A_4 net33_4 pass passB) tgateSimple_min
    A_tgate_5 (VDD VSS A_5 net33_5 pass passB) tgateSimple_min
    A_tgate_6 (VDD VSS A_6 net33_6 pass passB) tgateSimple_min
    A_tgate_7 (VDD VSS A_7 net33_7 pass passB) tgateSimple_min
    A_tgate_8 (VDD VSS A_8 net33_8 pass passB) tgateSimple_min
    A_tgate_9 (VDD VSS A_9 net33_9 pass passB) tgateSimple_min
    A_tgate_10 (VDD VSS A_10 net33_10 pass passB) tgateSimple_min
    A_tgate_11 (VDD VSS A_11 net33_11 pass passB) tgateSimple_min
    A_tgate_12 (VDD VSS A_12 net33_12 pass passB) tgateSimple_min
    A_tgate_13 (VDD VSS A_13 net33_13 pass passB) tgateSimple_min
    A_tgate_14 (VDD VSS A_14 net33_14 pass passB) tgateSimple_min
    A_tgate_15 (VDD VSS A_15 net33_15 pass passB) tgateSimple_min
    AND_0 (net33_0 net27_0 VDD VSS out_and_0 net40_0) AND
    AND_1 (net33_1 net27_1 VDD VSS out_and_1 net40_1) AND
    AND_2 (net33_2 net27_2 VDD VSS out_and_2 net40_2) AND
    AND_3 (net33_3 net27_3 VDD VSS out_and_3 net40_3) AND
    AND_4 (net33_4 net27_4 VDD VSS out_and_4 net40_4) AND
    AND_5 (net33_5 net27_5 VDD VSS out_and_5 net40_5) AND
    AND_6 (net33_6 net27_6 VDD VSS out_and_6 net40_6) AND
    AND_7 (net33_7 net27_7 VDD VSS out_and_7 net40_7) AND
    AND_8 (net33_8 net27_8 VDD VSS out_and_8 net40_8) AND
    AND_9 (net33_9 net27_9 VDD VSS out_and_9 net40_9) AND
    AND_10 (net33_10 net27_10 VDD VSS out_and_10 net40_10) AND
    AND_11 (net33_11 net27_11 VDD VSS out_and_11 net40_11) AND
    AND_12 (net33_12 net27_12 VDD VSS out_and_12 net40_12) AND
    AND_13 (net33_13 net27_13 VDD VSS out_and_13 net40_13) AND
    AND_14 (net33_14 net27_14 VDD VSS out_and_14 net40_14) AND
    AND_15 (net33_15 net27_15 VDD VSS out_and_15 net40_15) AND
ends AND16A
// End of subcircuit definition.

// Library name: Project
// Cell name: ALU4
// View name: schematic
subckt ALU4 A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 A_13 \
        A_14 A_15 B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_10 B_11 B_12 \
        B_13 B_14 B_15 VDD VSS out_0 out_1 out_2 out_3 out_4 out_5 out_6 \
        out_7 out_8 out_9 out_10 out_11 out_12 out_13 out_14 out_15 \
        out_last_0 out_last_1 out_last_2 out_last_3 out_last_4 out_last_5 \
        out_last_6 out_last_7 out_last_8 out_last_9 out_last_10 \
        out_last_11 out_last_12 out_last_13 out_last_14 out_last_15 \
        overflow sel0 sel1 sel2
    special_tgate_0 (VDD VSS VSS out_0 pass_7 passB_7) tgateSimple_min
    special_tgate_1 (VDD VSS VSS out_1 pass_7 passB_7) tgateSimple_min
    special_tgate_2 (VDD VSS VSS out_2 pass_7 passB_7) tgateSimple_min
    special_tgate_3 (VDD VSS VSS out_3 pass_7 passB_7) tgateSimple_min
    special_tgate_4 (VDD VSS VSS out_4 pass_7 passB_7) tgateSimple_min
    special_tgate_5 (VDD VSS VSS out_5 pass_7 passB_7) tgateSimple_min
    special_tgate_6 (VDD VSS VSS out_6 pass_7 passB_7) tgateSimple_min
    special_tgate_7 (VDD VSS VSS out_7 pass_7 passB_7) tgateSimple_min
    special_tgate_8 (VDD VSS VSS out_8 pass_7 passB_7) tgateSimple_min
    special_tgate_9 (VDD VSS VSS out_9 pass_7 passB_7) tgateSimple_min
    special_tgate_10 (VDD VSS VSS out_10 pass_7 passB_7) tgateSimple_min
    special_tgate_11 (VDD VSS VSS out_11 pass_7 passB_7) tgateSimple_min
    special_tgate_12 (VDD VSS VSS out_12 pass_7 passB_7) tgateSimple_min
    special_tgate_13 (VDD VSS VSS out_13 pass_7 passB_7) tgateSimple_min
    special_tgate_14 (VDD VSS VSS out_14 pass_7 passB_7) tgateSimple_min
    special_tgate_15 (VDD VSS VSS out_15 pass_7 passB_7) tgateSimple_min
    nop_tgate_0 (VDD VSS out_last_0 out_0 pass_0 passB_0) tgateSimple_min
    nop_tgate_1 (VDD VSS out_last_1 out_1 pass_0 passB_0) tgateSimple_min
    nop_tgate_2 (VDD VSS out_last_2 out_2 pass_0 passB_0) tgateSimple_min
    nop_tgate_3 (VDD VSS out_last_3 out_3 pass_0 passB_0) tgateSimple_min
    nop_tgate_4 (VDD VSS out_last_4 out_4 pass_0 passB_0) tgateSimple_min
    nop_tgate_5 (VDD VSS out_last_5 out_5 pass_0 passB_0) tgateSimple_min
    nop_tgate_6 (VDD VSS out_last_6 out_6 pass_0 passB_0) tgateSimple_min
    nop_tgate_7 (VDD VSS out_last_7 out_7 pass_0 passB_0) tgateSimple_min
    nop_tgate_8 (VDD VSS out_last_8 out_8 pass_0 passB_0) tgateSimple_min
    nop_tgate_9 (VDD VSS out_last_9 out_9 pass_0 passB_0) tgateSimple_min
    nop_tgate_10 (VDD VSS out_last_10 out_10 pass_0 passB_0) \
        tgateSimple_min
    nop_tgate_11 (VDD VSS out_last_11 out_11 pass_0 passB_0) \
        tgateSimple_min
    nop_tgate_12 (VDD VSS out_last_12 out_12 pass_0 passB_0) \
        tgateSimple_min
    nop_tgate_13 (VDD VSS out_last_13 out_13 pass_0 passB_0) \
        tgateSimple_min
    nop_tgate_14 (VDD VSS out_last_14 out_14 pass_0 passB_0) \
        tgateSimple_min
    nop_tgate_15 (VDD VSS out_last_15 out_15 pass_0 passB_0) \
        tgateSimple_min
    pass_tgate_0 (VDD VSS A_0 out_0 pass_6 passB_6) tgateSimple_min
    pass_tgate_1 (VDD VSS A_1 out_1 pass_6 passB_6) tgateSimple_min
    pass_tgate_2 (VDD VSS A_2 out_2 pass_6 passB_6) tgateSimple_min
    pass_tgate_3 (VDD VSS A_3 out_3 pass_6 passB_6) tgateSimple_min
    pass_tgate_4 (VDD VSS A_4 out_4 pass_6 passB_6) tgateSimple_min
    pass_tgate_5 (VDD VSS A_5 out_5 pass_6 passB_6) tgateSimple_min
    pass_tgate_6 (VDD VSS A_6 out_6 pass_6 passB_6) tgateSimple_min
    pass_tgate_7 (VDD VSS A_7 out_7 pass_6 passB_6) tgateSimple_min
    pass_tgate_8 (VDD VSS A_8 out_8 pass_6 passB_6) tgateSimple_min
    pass_tgate_9 (VDD VSS A_9 out_9 pass_6 passB_6) tgateSimple_min
    pass_tgate_10 (VDD VSS A_10 out_10 pass_6 passB_6) tgateSimple_min
    pass_tgate_11 (VDD VSS A_11 out_11 pass_6 passB_6) tgateSimple_min
    pass_tgate_12 (VDD VSS A_12 out_12 pass_6 passB_6) tgateSimple_min
    pass_tgate_13 (VDD VSS A_13 out_13 pass_6 passB_6) tgateSimple_min
    pass_tgate_14 (VDD VSS A_14 out_14 pass_6 passB_6) tgateSimple_min
    pass_tgate_15 (VDD VSS A_15 out_15 pass_6 passB_6) tgateSimple_min
    I31 (out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 out_8 out_9 \
        out_10 out_11 out_12 out_13 out_14 out_15 VDD VSS A_0 A_1 A_2 A_3 \
        A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 A_13 A_14 A_15 B_0 B_1 B_2 \
        B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_10 B_11 B_12 B_13 B_14 B_15 pass_5 \
        passB_5) OR16A
    I28 (VDD VSS addsub_passB addsub_pass) inv_8X
    I27 (VDD VSS net119 net115 addsub_passB) NAND2_big
    I26 (VDD VSS sel1 sel0 net115) XOR
    I25 (VDD VSS sel2 net119) inv_4X
    I18 (A_addsub_0 A_addsub_1 A_addsub_2 A_addsub_3 A_addsub_4 A_addsub_5 \
        A_addsub_6 A_addsub_7 A_addsub_8 A_addsub_9 A_addsub_10 \
        A_addsub_11 A_addsub_12 A_addsub_13 A_addsub_14 A_addsub_15 \
        B_addsub_0 B_addsub_1 B_addsub_2 B_addsub_3 B_addsub_4 B_addsub_5 \
        B_addsub_6 B_addsub_7 B_addsub_8 B_addsub_9 B_addsub_10 \
        B_addsub_11 B_addsub_12 B_addsub_13 B_addsub_14 B_addsub_15 pass_2 \
        Cout_0 Cout_1 Cout_2 Cout_3 Cout_4 Cout_5 Cout_6 Cout_7 Cout_8 \
        Cout_9 Cout_10 Cout_11 Cout_12 Cout_13 Cout_14 overflow \
        addsub_out_0 addsub_out_1 addsub_out_2 addsub_out_3 addsub_out_4 \
        addsub_out_5 addsub_out_6 addsub_out_7 addsub_out_8 addsub_out_9 \
        addsub_out_10 addsub_out_11 addsub_out_12 addsub_out_13 \
        addsub_out_14 addsub_out_15 VDD VSS) addsub16b_block
    I17 (A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 A_13 A_14 \
        out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 out_8 out_9 out_10 \
        out_11 out_12 out_13 out_14 out_15 B_0 B_1 VDD VSS pass_3 passB_3) \
        Shift4b
    I0 (pass_0 pass_1 pass_2 pass_3 pass_4 pass_5 pass_6 pass_7 passB_0 \
        passB_1 passB_2 passB_3 passB_4 passB_5 passB_6 passB_7 VDD VSS \
        sel0 sel1 sel2) _sub3
    I23_0 (VDD VSS A_0 A_addsub_0 addsub_pass addsub_passB) tgateSimple
    I23_1 (VDD VSS A_1 A_addsub_1 addsub_pass addsub_passB) tgateSimple
    I23_2 (VDD VSS A_2 A_addsub_2 addsub_pass addsub_passB) tgateSimple
    I23_3 (VDD VSS A_3 A_addsub_3 addsub_pass addsub_passB) tgateSimple
    I23_4 (VDD VSS A_4 A_addsub_4 addsub_pass addsub_passB) tgateSimple
    I23_5 (VDD VSS A_5 A_addsub_5 addsub_pass addsub_passB) tgateSimple
    I23_6 (VDD VSS A_6 A_addsub_6 addsub_pass addsub_passB) tgateSimple
    I23_7 (VDD VSS A_7 A_addsub_7 addsub_pass addsub_passB) tgateSimple
    I23_8 (VDD VSS A_8 A_addsub_8 addsub_pass addsub_passB) tgateSimple
    I23_9 (VDD VSS A_9 A_addsub_9 addsub_pass addsub_passB) tgateSimple
    I23_10 (VDD VSS A_10 A_addsub_10 addsub_pass addsub_passB) tgateSimple
    I23_11 (VDD VSS A_11 A_addsub_11 addsub_pass addsub_passB) tgateSimple
    I23_12 (VDD VSS A_12 A_addsub_12 addsub_pass addsub_passB) tgateSimple
    I23_13 (VDD VSS A_13 A_addsub_13 addsub_pass addsub_passB) tgateSimple
    I23_14 (VDD VSS A_14 A_addsub_14 addsub_pass addsub_passB) tgateSimple
    I23_15 (VDD VSS A_15 A_addsub_15 addsub_pass addsub_passB) tgateSimple
    I24_0 (VDD VSS B_0 B_addsub_0 addsub_pass addsub_passB) tgateSimple
    I24_1 (VDD VSS B_1 B_addsub_1 addsub_pass addsub_passB) tgateSimple
    I24_2 (VDD VSS B_2 B_addsub_2 addsub_pass addsub_passB) tgateSimple
    I24_3 (VDD VSS B_3 B_addsub_3 addsub_pass addsub_passB) tgateSimple
    I24_4 (VDD VSS B_4 B_addsub_4 addsub_pass addsub_passB) tgateSimple
    I24_5 (VDD VSS B_5 B_addsub_5 addsub_pass addsub_passB) tgateSimple
    I24_6 (VDD VSS B_6 B_addsub_6 addsub_pass addsub_passB) tgateSimple
    I24_7 (VDD VSS B_7 B_addsub_7 addsub_pass addsub_passB) tgateSimple
    I24_8 (VDD VSS B_8 B_addsub_8 addsub_pass addsub_passB) tgateSimple
    I24_9 (VDD VSS B_9 B_addsub_9 addsub_pass addsub_passB) tgateSimple
    I24_10 (VDD VSS B_10 B_addsub_10 addsub_pass addsub_passB) tgateSimple
    I24_11 (VDD VSS B_11 B_addsub_11 addsub_pass addsub_passB) tgateSimple
    I24_12 (VDD VSS B_12 B_addsub_12 addsub_pass addsub_passB) tgateSimple
    I24_13 (VDD VSS B_13 B_addsub_13 addsub_pass addsub_passB) tgateSimple
    I24_14 (VDD VSS B_14 B_addsub_14 addsub_pass addsub_passB) tgateSimple
    I24_15 (VDD VSS B_15 B_addsub_15 addsub_pass addsub_passB) tgateSimple
    add_tgate_0 (VDD VSS addsub_out_0 out_0 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_1 (VDD VSS addsub_out_1 out_1 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_2 (VDD VSS addsub_out_2 out_2 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_3 (VDD VSS addsub_out_3 out_3 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_4 (VDD VSS addsub_out_4 out_4 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_5 (VDD VSS addsub_out_5 out_5 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_6 (VDD VSS addsub_out_6 out_6 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_7 (VDD VSS addsub_out_7 out_7 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_8 (VDD VSS addsub_out_8 out_8 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_9 (VDD VSS addsub_out_9 out_9 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_10 (VDD VSS addsub_out_10 out_10 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_11 (VDD VSS addsub_out_11 out_11 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_12 (VDD VSS addsub_out_12 out_12 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_13 (VDD VSS addsub_out_13 out_13 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_14 (VDD VSS addsub_out_14 out_14 addsub_pass addsub_passB) \
        tgateSimple
    add_tgate_15 (VDD VSS addsub_out_15 out_15 addsub_pass addsub_passB) \
        tgateSimple
    I1 (A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 A_13 A_14 \
        A_15 B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_10 B_11 B_12 B_13 \
        B_14 B_15 VDD VSS out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 \
        out_8 out_9 out_10 out_11 out_12 out_13 out_14 out_15 pass_4 \
        passB_4) AND16A
ends ALU4
// End of subcircuit definition.

// Library name: Project
// Cell name: TB_ALUadd
// View name: schematic
reg_out_0 (CLK ALU_out_0 net043_0 out_0 vdd! 0) Register_pos_small
reg_out_1 (CLK ALU_out_1 net043_1 out_1 vdd! 0) Register_pos_small
reg_out_2 (CLK ALU_out_2 net043_2 out_2 vdd! 0) Register_pos_small
reg_out_3 (CLK ALU_out_3 net043_3 out_3 vdd! 0) Register_pos_small
reg_out_4 (CLK ALU_out_4 net043_4 out_4 vdd! 0) Register_pos_small
reg_out_5 (CLK ALU_out_5 net043_5 out_5 vdd! 0) Register_pos_small
reg_out_6 (CLK ALU_out_6 net043_6 out_6 vdd! 0) Register_pos_small
reg_out_7 (CLK ALU_out_7 net043_7 out_7 vdd! 0) Register_pos_small
reg_out_8 (CLK ALU_out_8 net043_8 out_8 vdd! 0) Register_pos_small
reg_out_9 (CLK ALU_out_9 net043_9 out_9 vdd! 0) Register_pos_small
reg_out_10 (CLK ALU_out_10 net043_10 out_10 vdd! 0) Register_pos_small
reg_out_11 (CLK ALU_out_11 net043_11 out_11 vdd! 0) Register_pos_small
reg_out_12 (CLK ALU_out_12 net043_12 out_12 vdd! 0) Register_pos_small
reg_out_13 (CLK ALU_out_13 net043_13 out_13 vdd! 0) Register_pos_small
reg_out_14 (CLK ALU_out_14 net043_14 out_14 vdd! 0) Register_pos_small
reg_out_15 (CLK ALU_out_15 net043_15 out_15 vdd! 0) Register_pos_small
reg_inB_0 (CLK B1 net049_0 Bclk_0 vdd! 0) Register_pos_test
reg_inB_1 (CLK B1 net049_1 Bclk_1 vdd! 0) Register_pos_test
reg_inB_2 (CLK B1 net049_2 Bclk_2 vdd! 0) Register_pos_test
reg_inB_3 (CLK B1 net049_3 Bclk_3 vdd! 0) Register_pos_test
reg_inB_4 (CLK B1 net049_4 Bclk_4 vdd! 0) Register_pos_test
reg_inB_5 (CLK B1 net049_5 Bclk_5 vdd! 0) Register_pos_test
reg_inB_6 (CLK B1 net049_6 Bclk_6 vdd! 0) Register_pos_test
reg_inB_7 (CLK B1 net049_7 Bclk_7 vdd! 0) Register_pos_test
reg_inB_8 (CLK B1 net049_8 Bclk_8 vdd! 0) Register_pos_test
reg_inB_9 (CLK B1 net049_9 Bclk_9 vdd! 0) Register_pos_test
reg_inB_10 (CLK B1 net049_10 Bclk_10 vdd! 0) Register_pos_test
reg_inB_11 (CLK B1 net049_11 Bclk_11 vdd! 0) Register_pos_test
reg_inB_12 (CLK B1 net049_12 Bclk_12 vdd! 0) Register_pos_test
reg_inB_13 (CLK B1 net049_13 Bclk_13 vdd! 0) Register_pos_test
reg_inB_14 (CLK B1 net049_14 Bclk_14 vdd! 0) Register_pos_test
reg_inB_15 (CLK B1 net049_15 Bclk_15 vdd! 0) Register_pos_test
reg_inA_0 (CLK A1 net055_0 Aclk_0 vdd! 0) Register_pos_test
reg_inA_1 (CLK A2 net055_1 Aclk_1 vdd! 0) Register_pos_test
reg_inA_2 (CLK A2 net055_2 Aclk_2 vdd! 0) Register_pos_test
reg_inA_3 (CLK A2 net055_3 Aclk_3 vdd! 0) Register_pos_test
reg_inA_4 (CLK A2 net055_4 Aclk_4 vdd! 0) Register_pos_test
reg_inA_5 (CLK A2 net055_5 Aclk_5 vdd! 0) Register_pos_test
reg_inA_6 (CLK A2 net055_6 Aclk_6 vdd! 0) Register_pos_test
reg_inA_7 (CLK A2 net055_7 Aclk_7 vdd! 0) Register_pos_test
reg_inA_8 (CLK A2 net055_8 Aclk_8 vdd! 0) Register_pos_test
reg_inA_9 (CLK A2 net055_9 Aclk_9 vdd! 0) Register_pos_test
reg_inA_10 (CLK A2 net055_10 Aclk_10 vdd! 0) Register_pos_test
reg_inA_11 (CLK A2 net055_11 Aclk_11 vdd! 0) Register_pos_test
reg_inA_12 (CLK A2 net055_12 Aclk_12 vdd! 0) Register_pos_test
reg_inA_13 (CLK A2 net055_13 Aclk_13 vdd! 0) Register_pos_test
reg_inA_14 (CLK A2 net055_14 Aclk_14 vdd! 0) Register_pos_test
reg_inA_15 (CLK A2 net055_15 Aclk_15 vdd! 0) Register_pos_test
I0 (Aclk_0 Aclk_1 Aclk_2 Aclk_3 Aclk_4 Aclk_5 Aclk_6 Aclk_7 Aclk_8 Aclk_9 \
        Aclk_10 Aclk_11 Aclk_12 Aclk_13 Aclk_14 Aclk_15 Bclk_0 Bclk_1 \
        Bclk_2 Bclk_3 Bclk_4 Bclk_5 Bclk_6 Bclk_7 Bclk_8 Bclk_9 Bclk_10 \
        Bclk_11 Bclk_12 Bclk_13 Bclk_14 Bclk_15 vdd! 0 ALU_out_0 ALU_out_1 \
        ALU_out_2 ALU_out_3 ALU_out_4 ALU_out_5 ALU_out_6 ALU_out_7 \
        ALU_out_8 ALU_out_9 ALU_out_10 ALU_out_11 ALU_out_12 ALU_out_13 \
        ALU_out_14 ALU_out_15 out_0 out_1 out_2 out_3 out_4 out_5 out_6 \
        out_7 out_8 out_9 out_10 out_11 out_12 out_13 out_14 out_15 \
        overflow C_0 C_1 C_2) ALU4
V1 (vdd! 0) vsource type=dc dc=5V
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
    sensfile="../psf/sens.output" checklimitdest=psf 
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub
